Trevor Floyd

The group that administers the Payment Card Industry Data Security Standard (PCI DSS) wants feedback about how the current version of the standard, released last October, is working.

Retailers, financial institutions and others in the payment industry will be able to submit online comments between July 1 and Nov. 1 about how to improve the PCI DSS 1.2 standard, the PCI Security Standards Council (SSC) said this week. Over the next few months, the PCI SSC will hold two "community meetings" - one in the U.S., the other in Europe - where stakeholders can also weigh in.

Those comments will be reviewed to see what changes need to be made in the next version of the standard, which is due out in the fall of 2010, said Robert Russo, general manager of the PCI SSC. In addition, the PCI SSC has commissioned PricewaterhouseCoopers P(wC) to review technologies such as end-to-end encryption, chip and PIN and tokenization to see whether these technologies should be made part of PCI requirements in the future, Russo said.

PCI standards were created by Visa, MasterCard and other major credit card brands and are administered by the PCI SSC. All companies that accept payment cards are required to implement the 12 high-level security controls prescribed under the standards. Larger companies face significantly tougher compliance requirements than smaller firms.

The request for comments and the review of new technologies by PwC come amid growing criticism of PCI from several quarters. Earlier this month, for instance, representatives from seven trade groups called for the standards to be developed in a more open manner. The letter, signed by representatives from the National Retail Federation, the Merchant Advisory Group, the National Restaurant Association and others, suggested that the PCI SSC adopt a standards writing process similar to those used by open standards bodies such as ANSI. The groups also recommended that retailers be given enough time to implement revisions and asked for a reduction in the number of requirements prescribed under PCI.

The letter added to a growing chorus of voices expressing concern about the burdensome and costly nature of PCI requirements and their effectiveness. At a House of Representatives hearing in April, U.S. lawmakers and representatives of the retail industry blasted PCI rules as being too static and wondered whether they were designed to protect card companies and banks from liability more than anything else.

Russo today pointed to the feedback process and the PwC review as efforts by the PCI security standard council to make the standards process inclusive, transparent and relevant. He noted that since its inception, the PCI council has relied heavily on input from its members and others in the payment industry to shape the standards.

The PCI council's move to ban retailers from using wireless networks based on the Wired Equivalent Privacy (WEP) protocol is one example where the council acted on the feedback from the community, he said. The PCI SSC has also eliminated or consolidated redundant requirements or tweaked requirements based on industry feedback.

"The changes in 1.2 were the result of feedback from the community at large and what they thought needed to be addressed with the standard," Russo said. "This is an opportunity for everyone to come together ... and discuss what needs to be changed for the good of the community or for the benefit of a particular vertical [industry]," he said.

Russo downplayed recent criticisms about the effectiveness of the standards and insisted that when implemented properly, they adequately protect companies against current threats. "At this point, we haven't seen anything in the standard that causes us concern," Russo said. He added that the PwC review was prompted by apparent interest in end-to-end encryption and other emerging technologies.

"What they will be doing is looking at these technologies and seeing what needs to be [included] for them to be considered for the standard," he said. The effort also includes seeing whether the technologies can be used as compensation controls in place of existing PCI requirements, he said.

Researchers have demonstrated a form of archive memory using carbon nanotubes that can theoretically store a trillion bits of data per square inch for a billion years.

The technology could easily be incorporated into today's silicon processing systems and it could be available in the next two years, a lead researcher said.

The scientists at the U.S. Department of Energy's Lawrence Berkeley National Laboratory and the University of California said the new technology can potentially pack thousands of times more data into one square inch of space than today's chips.

"We've developed a new mechanism for digital memory storage that consists of a crystalline iron nanoparticle shuttle enclosed within the hollow of a multiwalled carbon nanotube," said physicist Alex Zettl, who led this research.

Zettl, who was lead author of the paper published online by Nano Letters entitled " Nanoscale Reversible Mass Transport for Archival Memory," is perhaps best known for his work on creating the world's smallest radioin 2007, which is one ten-thousandth the width of a human hair.

Zettl said this latest nanotube breakthrough uses an iron nanoparticle, approximately 1/50,000th the width of a human hair, that in the presence of a low voltage electrical current can be shuttled back and forth inside a hollow carbon nanotube with remarkable precision.

The shuttle's position inside the tube can be read out directly via a simple measurement of electrical resistance, allowing the shuttle to function as a nonvolatile memory element with potentially hundreds of binary memory states.

"The shuttle memory has application for archival data storage with information density as high as one trillion bits per square inch and thermodynamic stability in excess of one billion years," Zettl said in a statement. "Furthermore, as the system is naturally hermetically sealed, it provides its own protection against environmental contamination."

Zettl said the low-voltage electrical write/read capabilities of the memory element in the electromechanical device allows for large-scale integration and should make for easy incorporation into today's silicon processing systems.

Zettl believes the technology could be on the market within the next two years.